Power Minimization with Multiple Supply Voltages and Multiple Threshold Voltages

Assigning gate supply voltage and transistor threshold voltages to a range of discrete values is a combinatorial problem. The optimization computational difficulty grows exponentially with the netlist size. Whereas, if the range of values is continuous, we show that the global optimum can be found in polynomial time. We show that posynomials can model variable supply and threshold voltages, with skewed gate drive strengths. The models have root mean square (RMS) errors of 10% or less compared to 0.13um SPICE data. With these models, geometric programming gives a convex problem formulation with globally optimal solutions for minimum delay, energy×delay, or power. For the examples considered, dual voltage and continuous voltage solutions reduce power by up to 22% compared to the optimal solution using single supply and thresholds voltages.